1. Field of the Invention
The present invention relates generally to the field of power amplifiers in multi-band communication systems. More particularly, the present invention relates to circuitry associated with such power amplifiers, such as harmonic filters, impedance load switching circuits, pre-distortion phase filters, and the like.
2. Description of the Related Art
Several digital air interface standards have been developed for providing efficient digital communication of voice, data, fax and text messages under the umbrella of “personal communications services” or PCS. Operational PCS systems, such as systems based on the GSM TDMA (Time Division Multiple Access) or IS-95 CDMA (Code Division Multiplex Access) air interface standards, are being implemented in the United States in the 1900 MHz frequency range. Meanwhile, existing analog (AMPS) and digital (D-AMPS) at 800 MHz cellular systems continue to operate. Thus, there are presently operating in the United States analog and digital cellular systems at 800 MHz and digital PCS systems at 1900 MHz. Mobile subscribers who desire to receive services from systems operating at 800 MHz and from systems operating at 1900 MHz must either use two different mobile transceivers or use a single “dual-band” mobile transceiver which can receive and transmit radio frequency (RF) signals in both frequency bands.
Power control is essential to the smooth operation of CDMA communication systems. Output power for each individual user should be adjusted dynamically to maximize the system capacity because there are many users sharing the frequency spectrum, which requires resolution of the near-far multiple-access in a spread-spectrum system. For this reason, a typical CDMA handset is operated under a varied output condition. Data obtained from the field indicates that a CDMA cellular phone handset spends approximately 95% of its time transmitting output power in a range of 10-30 dB lower than its maximum rated output power. Recognizing this fact, most CDMA handset power amplifiers have lower power (LP) and high power (HP) modes of operation. The purpose of this two-mode operation is to improve the efficiency performance at the LP mode.
FIG. 1 shows a diagram of wireless voice communication device 100, such as a typical mobile phone handset for cellular telephone use. The device 100 includes a microphone 102 for converting audio signals to electrical signals and a transmitter 104 for transmitting the electrical signals. Device 100 also includes receiver 112 connected to speaker 114. Transmitter 104 and receiver 112 normally share antenna 110, although separate antennas may instead be provided.
Transmitter 104 includes, inter alia, speech coder 120 for encoding the electrical voice signals, which are forwarded to modulator 122. Depending on the power mode and network used, modulator 122 mixes the coded signals to the appropriate frequency band. For example, modulator 122 shifts the signal to approximately 800 MHz in the case of CDMA or 1900 MHz in the case of Wideband CDMA (WCDMA). Power amplifier/load switch 124 amplifies and impedance matches the signal. The load switch portion of power amplifier/load switch 124 matches the outgoing signal to the required impedance and may also filter out various signal harmonics. Impedance matching increases amplifier power efficiency and filtering harmonics reduces undesired interference. Isolator 106 and receive/transmit duplexer 108 connect power amplifier/load switch circuit 124 and antenna 110. Using this series of components device 100 may transmit RF signals using antenna 110.
Receiver 112 obtains a received RF signal from antenna 110 via duplexer 108. RF receiver 130 prepares the received RF signal for demodulation. Demodulator 132 demodulates the received RF signal to output a demodulated signal, and speech decoder 134 decodes the demodulated signal to form an audio signal for reproduction on speaker 114.
A significant portion of the power in a wireless communication device is dissipated in the power amplifier (PA) (e.g., power amplifier/load switch 124) and the efficiency of a power amplifier is predominately determined by its output load design. There are two main factors affecting the output load design: the class of operation (e.g., class-A, -A/B, -B, -C, -E, etc.); and the load impedance at the fundamental and harmonic frequencies. In a typical PA design, the load is designed to achieve the best efficiency performance at its highest output power. For those power amplifiers that need to have low signal distortion (such as CDMA PA), there are the additional linearity constraints.
Wireless communication devices typically transmit RF signals at a plurality of power levels. The efficiency of the PA, however, significantly varies over the output power range. Typically, the PA is designed to maximize efficiency at higher output power levels because current drain efficiency of the PA becomes more significant at higher output power.
One technique to improve power efficiency switches the quiescent current of the PA in response to a PA output high power (HP)/low power (LP) mode control change. In the HP mode, the PA is biased with high quiescent current in order to maximize its output current swing. Similarly, in the LP mode, the PA is biased with low quiescent current in order to reduce current consumption.
Another circuit technique for improving the efficiency for varied output power system is load switching—i.e., the output load is adjusted in accordance with the output power requirements. In a switched load circuit design, the operational efficiency of a power amplifier is dependent on load impedance. A PA generally designed for maximum output power operation, i.e., HP mode, “sees” a low impedance load. This is necessary to maximize the device's current swing. An undesirable side effect of providing this low impedance is that it often leads to a degraded efficiency when the output power level is low.
Load switching is known for multi-mode handsets that operate in several frequency bands. The power amplifiers in these devices, however, are optimized for the high power mode with the low power mode operations, when present, being relatively inefficient. Several approaches for multi-band power amplifier designs based on the discussed design approaches are described next.
U.S. Pat. No. 5,774,017 (issued to Adar) (henceforth referred to as the '017 patent), teaches a multiple-band amplifier. The '17 patent discloses a GaAs MMIC dual-band amplifier for wireless communications for operation at either the 800 MHz or the 1900 MHz band and it provides desired gain and input and output impedance. Switching impedance networks are used at the input and output of the amplifier to provide matching input impedance and desired output impedance for operation in the two bands. Switching impedance networks are also used between any successive stages of the amplifier to provide proper interstage impedance. The dual band amplifier includes a bias control circuit which biases the amplifier to operate in A, B, AB, or C mode. The amplifier can be used for the AMPS 800 or the GSM 900 operation or any other cellular operation such as the PCS 1900 and it can be switched between the two operations by simply applying a proper control signal to the amplifier.
U.S. Pat. No. 6,188,877 (issued to Boesch et al.) (henceforth referred to as the '877 patent) describes a dual-band, dual-mode power amplifier with reduced power loss. The disclosed power amplifier circuit has a driver amplifier stage including a low band driver amplifier and a high band driver amplifier. A final amplifier stage includes a linear mode amplifier for amplifying digitally modulated signals and a saturated (nonlinear) mode amplifier for amplifying frequency modulated (analog) signals. A switching network interconnects the driver amplifier stage and the final amplifier stage. Depending on the desired mode of operation, an appropriate driver amplifier can be coupled to an appropriate final amplifier to most effectively and efficiently amplify analog or digital RF signals in either of a plurality of frequency bands. A matching circuit is coupled to the linear mode final amplifier for impedance matching and for separating D-AMPS (800 MHz band) and PCS (1900 MHz band) digital signals. A power impedance matching circuit is coupled to the output of the saturated mode final amplifier. In one embodiment, an isolator is coupled to the output of one or more of the low band or high band outputs of the duplex matching circuit. In the low band analog path, a duplexer is provided ahead of the coupling means for reducing the RF power requirements on the coupling means. The switching network and input filter stage may precede a driver amplifier stage.
U.S. Pat. No. 6,215,359 (issued to Peckham et al.) (henceforth referred to as the '359 patent) teaches impedance matching for a dual band power amplifier. It describes using a switched capacitor circuit to accomplish GSM/DCS dual band load impedance switching and high level harmonic suppression. The '359 patent discloses an exciter matching circuit, interstage matching circuit, and harmonic filter matching circuit to match impedances at the input to a two-stage PA, between the first stage and the second stage of the PA, and at the output of the PA for more than one frequency band of interest. In a GSM/DCS dual band radiotelephone, the matching circuits provide low return loss at 900 MHz when the dual band transmitter is operating in the GSM mode. The harmonic filter matching circuit also filters out signals at 1800 MHz, 2700 MHz, and high order harmonics. When the dual band transmitter is in DCS mode, however, the matching circuits provide a low return loss at 1800 MHz and filter out signals at 2700 MHz and harmonics of 1800 MHz.
FIG. 2 shows an output matching circuit 200 that operates in conjunction with power amplifier 202. The output matching circuit 200 of FIG. 2 is similar to that disclosed in U.S. Pat. No. 6,243,566 to Peckham et al. Output matching circuit 200 includes signal input node N21 that receives the output from power amplifier 202. First transmission line TL21 is connected between node N21 and second node N22 that is internal to circuit 200. Second transmission line TL22 is connected between second node N22 and third node N23. First capacitor C21 is connected between second node N22 and ground and second capacitor C22 is connected between third node N23 and fourth node N24, which may be an input to the next element or circuit, such as an isolator, in the overall device. Capacitor C22 acts as a DC blocking capacitor, allowing RF signals to pass therethrough.
The impedance of output matching circuit 200 is determined by the characteristics of the transmission lines and the capacitance of capacitor C21, which is configured to improve the efficiency at the high power levels. This choice of capacitor C21 to lower the impedance seen by power amplifier 202 also results in more effective treatment of interference. Such improvement at high power levels, however, also results in reduced average power efficiency due to reduced efficiency in the low power mode, which was noted to be the mode in which 95% of time was spent by CDMA sets. Thus, the typical design of power amplifiers, although optimized for high power mode, actually results in reduced battery life.
FIG. 3 shows load switching circuit 300 that operates in conjunction with power amplifier 302. Again, for simplicity, only circuit 300 is shown in detail, it being understood that more than one type of amplifier may work with circuit 300. The load switching circuit 300 of FIG. 2 is not unlike that disclosed in FIG. 13 of U.S. Pat. No. 5,774,017 to Adar showing each capacitor C31, C32 connected to a separate switch, the two switches acting in a complementary and mutually exclusive manner to provide different load impedances for different frequency bands of operation.
Circuit 300 includes signal input node N31 that receives the output from power amplifier 302. A first transmission line TL31 is connected between node N31 and second node N32, which is internal to circuit 300. Second transmission line TL32 is connected between second node N32 and third node N33. First capacitor C31 is connected between second node N32 and switch SW31 and second capacitor C32 is connected between third node N33 and switch SW31. Circuit 300 also includes third capacitor C33 connected between third node N33 and fourth node N34, which may be an input to the next element or circuit, such as an isolator, in the overall device. Capacitor C33 acts as a DC blocking capacitor, allowing RF signals to pass therethrough.
Switch SW31 is an electronic switch connecting either C31 or C32 to ground at any given instant, depending on frequency band selector input 304. Switch SW31 is typically implemented by a transistor circuit which has two mutually exclusive outputs driven by frequency band selector input 304 from a logic circuit, a processor (not shown), or other such known device.
In response to a frequency band selector input signal of a first type (e.g., low voltage), capacitor C31 is coupled to ground via switch SW31 and capacitor C32 is unconnected to ground. Transmission lines TL31, TL32 and capacitor C31 operate in conjunction with power amplifier 302 to provide a first predetermined output impedance suitable for operation at 1900 MHz, for example.
Similarly, in response to a mode signal of a second type (e.g., high voltage), capacitor C32 is coupled to ground via switch SW31 and capacitor C31 is unconnected to ground. In such case, transmission lines TL31, TL32 and capacitor C32 operate in conjunction with power amplifier 302 to provide a second predetermined output impedance suitable for operation at a second frequency band such as for example at 800 MHz.
The prior art does not teach or suggest selecting the output matching impedance to improve operation at an output power levels other than at high power even though CDMA phones actually spend an overwhelming amount of their operational time in relatively lower power modes.
The high power performance of a power amplifier is often compromised by the distortion or noise generated as a result of such an operation. Using a predistortion linearizer adversely impacts the performance in lower power modes due to the weak input signals. A useful discussion of predistortion linearizers is found in “Diode Predistortion Linearization for Power Amplifier RFICs in Digital Radios.” by Christopher B. Haskins presented in the part fulfillment of the Master of Science degree at Virginia Polytechnic Institute and State University on Apr. 17, 2000 and is herein incorporated by reference in its entirety. Such limitations on the use of predistortion linearizers require that a choice be made between superior performance in a high power mode and the performance in a lower power mode.